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ADE7854/ADE7858/ADE7868/ADE7878
The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the
LPOILVL register as LPOIL[2:0]/8 of full scale. Every time
one phase current becomes greater than the threshold, a
counter is incremented. If every phase counter remains below
LPLINE[4:0] + 1 at the end of the measurement period, then
the IRQ0 pin is triggered low. If a single phase counter becomes
greater or equal to LPLINE[4:0] + 1 at the end of the measure-
ment period, the IRQ1 pin is triggered low. Figure 24 illustrates
how the ADE7868 / ADE7878 behave in PSM2 mode when
LPLINE[4:0] = 2 and LPOIL[2:0] = 3. The test period is three
50 Hz cycles (60 ms), and the Phase A current rises above the
LPOIL[2:0] threshold three times. At the end of the test period,
the IRQ1 pin is triggered low.
LPLINE[4:0] = 2
Data Sheet
The PSM2 level threshold comparison works based on a peak
detection methodology. The peak detect circuit makes the
comparison based on the positive terminal current channel
input, I AP , I BP , and I CP (see Figure 25). In case of differential
inputs being applied to the current channels, Figure 25 shows
the differential antiphase signals at each of the current input
terminals, I xP and I xN , and the net differential current, I xP – I xN .
The I 2 C or SPI port is not functional during this mode. The PSM2
mode reduces the power consumption required to monitor the
currents when there is no voltage input and the voltage supply
of the ADE7868 / ADE7878 is provided by an external battery. If
the IRQ0 pin is triggered low at the end of a measurement period,
this signifies all phase currents stayed below threshold and,
therefore, there is no current flowing through the system.
At this point, the external microprocessor sets the ADE7868 /
IA CURRENT
LPOIL[2:0]
THRESHOLD
ADE7878 into Sleep Mode PSM3. If the IRQ1 pin is triggered
low at the end of the measurement period, this signifies that at
least one current input is above the defined threshold and
current is flowing through the system, although no voltage is
present at the ADE7868 / ADE7878 pins. This situation is often
called missing neutral and is considered a tampering situation,
at which point the external microprocessor sets the ADE7868 /
ADE7878 into PSM1 mode, measures the mean absolute values
PHASE
COUNTER = 1
PHASE
COUNTER = 2
PHASE
COUNTER = 3
of phase currents, and integrates the energy based on their values
and the nominal voltage.
It is recommended to use the ADE7868/ADE7878inPSM2
IRQ1
Figure 24. PSM2 Mode Triggering IRQ1 Pin for LPLINE[4:0] = 2
(50 Hz Systems)
+V p-p/2
+V p-p
I xP
mode when Bits[2:0] (PGA1[2:0]) of the gain register are equal
to 1 or 2. These bits represent the gain in the current channel
datapath. It is not recommended to use the ADE7868 / ADE7878
in PSM2 mode when the PGA1[2:0] bits are equal to 4, 8, or 16.
PSM3—SLEEP MODE (ALL PARTS)
–V p-p/2
+V p-p/2
I xP – I xN
The sleep mode is available on all parts ( ADE7854 , ADE7858 ,
ADE7868 , and ADE7878 ). In this mode, the ADE78xx has most
of its internal circuits turned off and the current consumption is
I xN
–V p-p/2
I xP
–V p-p
(a)
PEAK DETECT CIRCUIT
TAMPER
INDICATION
at its lowest level. The I 2 C, HSDC, and SPI ports are not func-
tional during this mode, and the RESET, SCLK/SCL, MOSI/SDA,
and SS/HSA pins should be set high.
V REF
(b)
Figure 25. PSM2 Low Power Mode Peak Detection
Rev. H | Page 24 of 100
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